In operation, the memory plane of a non-volatile memory may be subject to short-circuits, for example, between the word-line and the substrate, owing notably to the large difference in potential applied during the erase operation. These short-circuits may be linked to a breakdown of the tunnel oxide or to a breakdown of the insulating spacers flanking the gate regions.
This may then result in defects in some sectors or in some rows of the non-volatile memory.
Row redundancy mechanisms exist which, when a defective row is detected, provide a replacement for this defective row by a redundant row.
One example of a redundancy mechanism for sectors of a non-volatile memory is, for example, described in the U.S. Patent Publication No. 2004/0130953.